AXI 1G Ethernet Reference Designs

This is the documentation for the AXI 1G Ethernet reference designs for the Ethernet FMC Max.

User Guide

• Description
  • Hardware Platforms
  • Software
• Hardware design
  • Ethernet FMC Max
  • Overview
  • Zynq UltraScale+ designs
  • Versal designs
  • MicroBlaze designs
  • Regenerating the diagrams
• Requirements
  • List of supported boards
• Build instructions
  • Source code
  • License requirements
  • Target designs
  • Cross-platform build runner
• Stand-alone lwIP Echo Server
  • Requirements
  • Build
  • Run the application
  • Expected output
  • UART settings
  • IP address
  • Test the echo server
  • Change the target port
  • Troubleshooting
• PetaLinux
  • Requirements
  • How to build
  • Boot a MicroBlaze design (auboard, kcu105_hpc, vcu118_fmcp)
  • Boot from SD card (Zynq UltraScale+ and Versal)
  • Boot via JTAG
  • UART terminal
  • Port configurations
  • Example Usage
• Yocto
  • Requirements
  • Build
  • Prepare the SD card
  • Boot
  • Log in
  • Use and test the ports
  • What the Yocto BSPs add
  • Troubleshooting
• Using and testing the ports in Linux
  • What you need
  • Identify the ports
  • Bring a port up
  • Check the link
  • Speed negotiation
  • Ping
  • Throughput with iperf3
  • Multiple ports on one network
  • If a port does not work
• Advanced: project structure and customization
  • Repository layout
  • Target naming
  • config/data.json and config/update.py
  • Build runner
  • Vivado side
  • Vitis side
  • PetaLinux side
  • Yocto side
  • Modifications layered on the stock BSPs
  • Where build outputs land
• Troubleshooting
  • Build failures
  • Ports not working
  • PetaLinux issues
  • Yocto issues
  • Dropped pings/packets
• Revision History
  • 2025.2
  • 2024.1