AXI 1G Ethernet Reference Designs

This is the documentation for the AXI 1G Ethernet reference designs for the Ethernet FMC Max.

User Guide

• Description
  • Hardware Platforms
  • Software
• Requirements
  • List of supported boards
• Build instructions
  • Source code
  • License requirements
  • Target designs
  • Windows users
  • Linux users
• Stand-alone lwIP Echo Server
  • Building the Vitis workspace
  • Run the application
  • UART settings
  • IP address
  • Change the target port
  • Example usage
• PetaLinux
  • Requirements
  • How to build
  • Boot a MicroBlaze design (auboard, kcu105_hpc, vcu118_fmcp)
  • Boot from SD card (Zynq UltraScale+ and Versal)
  • Boot via JTAG
  • UART terminal
  • Port configurations
  • Example Usage
• Advanced: project structure and customization
  • Repository layout
  • Target naming
  • config/data.json and config/update.py
  • Make-driven build flow
  • Vivado side
  • Vitis side
  • PetaLinux side
  • Modifications layered on the stock BSPs
  • Where build outputs land
• Troubleshooting
  • Build failures
  • PetaLinux issues
• Revision History
  • 2025.2
  • 2024.1